1. Field of the Invention
The invention relates to an N-bit constant coefficient adder/subtractor.
2. Description of the Related Art
A constant coefficient adder/subtractor circuit has one operand that is a constant. In field programmable gate arrays (FPGAs) based on look-up tables (LUTs), generally two techniques are used for the implementation of such adder/subtractor. The first technique uses an arithmetic mode for implementation, as shown in FIG. 1, and the second uses LUTs in normal mode.
In LUT based FPGAs, for the implementation of adder/subtractor and likewise circuits, a special mode called arithmetic mode is supported. A 4-input LUT configured in arithmetic mode is capable of generating two specific functions as output (LUT out and Carry Out). Generally one function is used for computation of sum/difference bit and the other one for the computation of carry/borrow. In this mode, three inputs arrive through normal routing and one through carry chain (i.e. carry out of previous LUT in the LUT array).
This technique uses a ripple carry implementation of an adder as shown in FIG. 2. The delay of the circuit is directly dependant on the number of stages through which the carry is propagated. Hence, the delay is directly proportional to the size of inputs and the delay of carry chains. Since, these carry chains are extremely fast, this implementation is well suited for LUT based FPGAs. Thus, the delay encountered in the implementation of an N-bit adder/subtractor is proportional to N+1. The same approach is used for a constant coefficient adder/subtractor.
However, the approach suffers with a drawback. Many of the post mapping optimization algorithms that can be run on LUT level net list for area/delay reduction cannot be applied on LUTs that are configured in arithmetic mode, due to the simultaneous generation of two functions from a single LUT. Thus, the advantage that could be achieved in terms of area/delay by the optimization algorithm is not obtained.
Further, the arithmetic mode uses extra logic besides the LUT. It also employs a dedicated carry chain to connect the carry output of one LUT with the carry input pin of the next LUT in the LUT array. Thus, two of the three inputs arrive through normal routing and one arrives through the carry chain (i.e. carry out of the previous LUT in the LUT array). This approach implements N-bit constant coefficient adder/subtractor in N LUTs, if carry tap out is available and in N+1 LUTs in absence of a carry tap out feature.
FIG. 3 shows another approach that implements constant coefficient addition/subtraction without using arithmetic mode while supporting post-mapping optimization. The delay encountered in this implementation for an N-bit adder/subtractor is proportional to an N/3 delay of routing resources used. This technique however, suffers from a serious drawback. The number of 4-input LUTs required to implement an N-bit adder/subtractor, is at least (N+N/3). Thus, this kind of implementation requires almost 33% more LUTs as compared to the previous approach. Hence, even if this implementation leaves scope for optimization, no significant gain can be achieved in terms of area.
Besides, the LUT logic is not fully utilized, as N/4 LUTs use only 2 of their inputs and another N/4 LUTs use only 3 of their inputs.
Moreover, for implementation of N-bit dynamic addition/subtraction as shown in FIG. 4, the number of 4-input LUTs requirement reaches to (N+ceil (N/2)-1). Besides this, the implementation makes non-uniform utilization of LUT logic (one third of the LUTs are underutilized).